A low power frequency synthesizer for 60-GHz wireless personal area networks

Nawreen Khan, Masum Hossain, K. L.Eddie Law

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


In this brief, a 60-GHz frequency synthesizer for wireless personal area networks is designed using 0.13- μm CMOS technology. The synthesizer operates at 60 GHz with phase noises of -98, -117, and -128 dBc/Hz at 1-, 10-, and 40-MHz frequency offsets, respectively. The 60-GHz clock is generated by combining a phase-locked loop (PLL) and an injection-locked oscillator. The PLL provides frequency tuning of the 60-GHz voltage-controlled oscillator (VCO) using replica tuning. A pulse train is generated using a novel passive delay-locked loop and a CMOS pulse generator. This pulse train is then used for filtering the phase noise of 60-GHz VCO up to a high offset frequency. The total power consumption of the frequency synthesizer is 57 mW with a 1.2-V power supply.

Original languageEnglish
Article number6033058
Pages (from-to)622-626
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number10
Publication statusPublished - Oct 2011
Externally publishedYes


  • Delay-locked loop (DLL)
  • edge combiner
  • frequency synthesizers
  • injection-locked oscillator (ILO)
  • phase-locked loop (PLL)


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