Automatic synthesis of IIR SC multistage decimators

Cheong Ngai, R. P. Martins

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)


This paper presents an automated system for- the design of IIR SC multistage decimators. Through the integration of different existing programs it provides a user-friendly interface that allows the implementation of IIR SC decimators from the top filter specifications down to the circuit layout. It allows the automated design of a cascade of decimator stages in order to obtain a sufficiently high ratio between the sampling frequency and the maximum signal frequency of interest, and also simplifies the circuit through the minimization of the silicon area. Two design examples are given to demonstrate the feasibility of this approach.

Original languageEnglish
Pages (from-to)III287-III290
JournalMidwest Symposium on Circuits and Systems
Publication statusPublished - 2004
EventThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan
Duration: 25 Jul 200428 Jul 2004


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