Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures

Ngai Cheong, R. P. Martins

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages9-12
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
Publication statusPublished - 1999
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 23 Aug 199925 Aug 1999

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/TerritoryKorea, Republic of
CitySeoul
Period23/08/9925/08/99

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