Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures

Ngai Cheong; R. P. Martins

doi:10.1109/APASIC.1999.824012

Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures

Ngai Cheong
, R. P. Martins

Faculty of Applied Sciences

University of Macau

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	9-12
Number of pages	4
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824012
Publication status	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 23 Aug 1999 → 25 Aug 1999

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	23/08/99 → 25/08/99

Access to Document

10.1109/APASIC.1999.824012

Cite this

Cheong, N., & Martins, R. P. (1999). Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 9-12). Article 824012 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824012

@inproceedings{3d01724560704620a32f5b16ece03862,

title = "Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures",

abstract = "This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.",

author = "Ngai Cheong and Martins, \{R. P.\}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",

year = "1999",

doi = "10.1109/APASIC.1999.824012",

language = "English",

isbn = "0780357051",

series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "9--12",

booktitle = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

address = "United States",

}

Cheong, N & Martins, RP 1999, Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824012, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 9-12, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 23/08/99. https://doi.org/10.1109/APASIC.1999.824012

Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures. / Cheong, Ngai; Martins, R. P.
AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 9-12 824012 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.

AB - This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.

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U2 - 10.1109/APASIC.1999.824012

DO - 10.1109/APASIC.1999.824012

M3 - Conference contribution

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SN - 0780357051

SN - 9780780357051

T3 - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

SP - 9

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BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999

Y2 - 23 August 1999 through 25 August 1999

ER -

Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures

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