TY - JOUR
T1 - A novel algorithm for automated optimum design of IIR SC decimators
AU - Ngai, Cheong
AU - Martins, Rui P.
AU - Franca, José E.
N1 - Funding Information:
Manuscript received March 31, 2001; revised March 7, 2002. This work was supported by the University of Macau. This paper was recommended by Associate Editor A. Baschirotto. C. Ngai is with the Computer Studies Program, Macao Polytechnic Institute, Macao, 519020 China (e-mail: [email protected]). R. P. Martins is with the Department of Electrical and Electronics Engineering, University of Macau, Macao, China on leave from Instituto Superior Tecnico (IST), 1049-001 Lisboa, Portugal (e-mail: [email protected]). J. E. Franca is with the Integrated Circuits and Systems Group, Department of Electrical and Computer Engineering, Instituto Superior Tecnico (IST), 1049-001 Lisboa, Portugal (e-mail: [email protected]). Publisher Item Identifier 10.1109/TCSII.2002.801208.
PY - 2002/4
Y1 - 2002/4
N2 - This brief presents a novel algorithm for optimizing the design of infinite-impulse response (IIR) switched.capacitor (SC) decimators. It is implemented with a computer-assisted iterative methodology to achieve minimum capacitance spread and usually leading also to the minimization of the total capacitor area, while considering scaling for maximum signal handling capability. A linear/nonlinear programming method is adopted for optimum adjustment of the capacitance values, within a specific decimator structure and a finite number of iterations. Several examples of automatic and optimum design of second-order IIR SC decimators are presented, together with a comparison against previous designs, obtained for the same circuits through the use of traditional methods.
AB - This brief presents a novel algorithm for optimizing the design of infinite-impulse response (IIR) switched.capacitor (SC) decimators. It is implemented with a computer-assisted iterative methodology to achieve minimum capacitance spread and usually leading also to the minimization of the total capacitor area, while considering scaling for maximum signal handling capability. A linear/nonlinear programming method is adopted for optimum adjustment of the capacitance values, within a specific decimator structure and a finite number of iterations. Several examples of automatic and optimum design of second-order IIR SC decimators are presented, together with a comparison against previous designs, obtained for the same circuits through the use of traditional methods.
KW - Automated optimum design
KW - Infinite-impulse response (IIR) switched-capacitor (SC) decimator
KW - Linear/nonlinear programming
UR - https://www.scopus.com/pages/publications/0036544768
U2 - 10.1109/TCSII.2002.801208
DO - 10.1109/TCSII.2002.801208
M3 - Article
AN - SCOPUS:0036544768
SN - 1057-7130
VL - 49
SP - 293
EP - 296
JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
IS - 4
ER -