ATM multiplexers and output port controllers with distributed control and flexible queueing disciplines

In this paper, we present a novel design concept for constructing high-speed output port controllers for ATM switches, and statistical multiplexers. The newly proposed concept provides an external framework in which the internal hardware designs can be modified to achieve a specific quality of service. Two distributed control designs are provided, namely the fully shared buffer and partially shared buffer architectures. The fully shared buffer architecture can provide the push-out mechanism or complete buffer sharing queueing discipline which gives the best loss and delay performances for incoming cell stream with static priority.