Interactive IIR SC multirate compiler applied to multistage decimator design

This paper proposes an interactive architecture compiler for SC multirate circuits that allows the automated design from the frequency specifications to the building block implementation, applied to the design and synthesis of multistage SC decimators. The compiler provides a library of different topologies that comprises a few independent multi-decimation building blocks. New building blocks defined by the users are also available for the design of a specific stage. A design example of a 7th order SC decimator illustrates the efficient synthesis of the corresponding resulting circuits that achieve the required anti-aliasing amplitude responses with respect to the speed requirements of the operational amplifiers and also the minimum capacitance spread and total capacitor area.