Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures

This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.